The present disclosure relates to a multi-core CPU system, and, more particularly, to a multi-core central processing unit (CPU) system which may adjust characteristics including a size and latency of a level 2 (L2) cache that may be accessed by operation cores according to a layout position of the operation cores and devices having the same.
A cache is a memory used to reduce average time taken for a CPU to access a main memory. The cache stores data frequently used and its associated address corresponding to a main memory.
The cache may be divided into a level 1 (L1) primary cache and a L2 secondary cache according to memory hierarchy thereof. As the size (or capacity) of the L2 cache increases, the latency of a core accessing the L2 cache also increases. In addition, the size of the L2 cache increases as the number of cores increases, so that the latency of each core accessing the L2 cache also increases. When the latency increases, performance of the multi-core CPU system including the cores is deteriorated.